System on Chip
Capteur + Algorithme intégré sur puce

At first sight, it seems desirable to integrate the sensor and the recognition engine on the same chip so you have a full integrated system: everything is done on the chip. I already published my thoughs in 1999 (J.F. Mainguet, M. Pegulu and J.B. Harris, " Fingerprint recognition based on silicon chips" Future Generation of Computer Systems 16 (2000), Elsevier, pp. 403-415 (submitted March 1999)) and here is an extract:

5.3. Cost of the process may limit integration

Fingerprint sensing typically requires a resolution of about 500 dpi; that is, a pixel pitch of 50 mm. Actual CMOS processes in production are 0.35 mm and smaller: these are too accurate for a fingerprint sensor, and are not inexpensive. Therefore, manufacturers of silicon fingerprint sensors tend to use old technologies (e.g. 0.8 mm, 6” wafers) to reduce the cost, as these technologies have a much lower cost per square mm.

A problem appears when one tries to integrate more functions on the same chip (to lower the overall cost). For instance, assume that we want to combine the microprocessor that performs the minutia extraction together with the sensor. Generally, the microprocessor requires an expensive (lower micron) process in order to have a powerful chip that processes data within, let us say, 1 s (people hate to wait). If the (low) cost of the sensor process is 1 unit per mm2, then the cost of the microprocessor process is 5 units per mm2, because at least three generations separate the two processes (here, we are comparing a 0.8 mm process with 0.25 mm).

Cost
(in arbitrary units)
sensor
(1 per mm2)
processor
(5 per mm2)
two-chip solution one-chip solution
square sensor 200 mm220010004001200
linear sensor 40 mm240200240440
processor 40 mm2-200

Remember that at the same time, the processor area, for the same function, can be roughly reduced by a factor of .0:8=0:25/2 D 10 (in fact, it is more than that when we consider other parameters such as interconnect density), by moving between processes. This is why the progress of microelectronics is so attractive.

However, this scheme does not work for a fingerprint sensor, because the size of the finger will not vary! So, we just increase the cost of the sensor by using the latest process.

This is why a two-chip solution, separated into processor and sensor, will prevail in the medium term, as manufacturers wait for the new technologies today to become old (and less expensive) tomorrow, to reduce this dramatic cost effect.

Another problem with integration is the fact that the algorithm is burned in the silicon. Once done, you cannot modify it, or at best you can alter some parameters in a flash RAM (which is expensive, but well, you will need some permanent memory somewhere to store the template) and so, if you have a bug or some enhancements, you need to release a new chip with a new maskset, so a new product, and this process is very expensive. You can do that only if you have some a good ROI (return on investment), and you need to produce at least several millions of pieces to reach that. It is scheduled in the next years to reach huge production levels, and so maybe we will see such SoC.

An alternate solution is NOT having the sensor on silicon (so you have not this problem). This is the case for some sensors that require a silicon companion chip, and this situation is a little bit more advantageous for this problem. But nothing is perfect: when you have several pieces to gather (sensor + silicon chip), then you have to pay more for the assembly and packaging...

Well, it seems that no breakthrough happened, and the situation still remains the same: the cost of the silicon is still driving this issue, and there are only a few System-on-Chip realized by some R&D laboratories, but no SoC in production.

I confess that it was quite easy to predict...


NTT

  • (1999) NTT Microsystem Integration Laboratories
  • A Single-Chip Fingerprint Sensor and Identifier (Shigematsu & als)
  • (2002) A 500 dpi 224/spl times/256-pixel single-chip fingerprint identification LSI with pixel-parallel image enhancement and rotation schemes Shigematsu, S. ; Fujii, K. ; Morimura, H. ; Hatano, T.
  • (2002) A 500dpi 224x256pixel single-chip fingerprint identification LSI with pixel-parallel image enhancement and rotation schemes and rotation schemes Shigematsu, S. ; Fujii, K. ; Morimura, H. ; Hatano, T.
  • NTT Low Energy Labs (1999)

    Dortmund univ.

  • (2000) Capacitive CMOS fingerprint sensor with on-chip parallel signal processing Stephan Jung.
    prototype 50x60 pixels @ 330dpi
  • (2000) Intelligent CMOS fingerprint sensors Jung & als.

  • Yonsei University

  • (2004) A CMOS Integrated Capacitive Fingerprint Sensor With 32-bit RISC Microcontroller Seung-Min Jung
  • Yonsei SoC Seung-Min Jung

    NTT

  • (2004) Single-chip fingerprint identification LSI

  • KAIST

  • (2005) A 200×160 Pixel CMOS Fingerprint Recognition SoC with Adaptable Column-Parallel Processors Seong-Jin Kim
  • KAIST SoC from Seong-Jin Kim

    Authentec

  • (2006 Jan) Authentec announced that the 1610 chip has an "integrated matcher". It is likely a partial solution, not a full recognition system.

  • Synaptics

  • (2015 Jul) Synaptics Announces World’s First Match-in-Sensor Fingerprint Authentication Technology.
    The first? Really? Ah! marketing guys...
    Match-in-Sensor™ fingerprint authentication technology doesn't mean that everything is done on the chip: the image processing may be done externally (try to take into account rotations for instance, or some filters, this is taking heavy resources). But well, considering that the image size is very small, let's take that as a full system on chip. So there are some security problem with some (secret) key management: answering "yes/no" is not enough, you have to check if you are talking with a real trusted fingerprint sensor. And we cannot say that the Synaptics solution is very clear about that. But it is already better to have the matching on chip, for sure. It will be harder to access the chip than the operating system of the (connected) host.